This invention relates generally to analog integrated circuits, and more particularly to circuits and methods for trimming networks, such as resistive networks, of analog integrated circuits.
Networks (including resistive, capacitive, inductive, and current source networks) are commonly used in analog integrated circuits. For example, resistive networks are commonly used to provide desired reference voltage levels. A resistive network can simply include the series connection of a number of resistive elements between the nodes of a voltage source, or may be a more complex structure including switches, gates, etc. Typically, the voltage source provides a known voltage output V.sub.cc of five or three volts dc with respect to ground. The topmost node of the resistive network is therefore typically at about V.sub.cc, and the bottom most node of the resistive network is typically at about ground. Intermediate nodes of the resistive network, i.e. nodes between the various resistive elements, will have a voltage level somewhere between ground and V.sub.cc. Therefore, a resistive network of a prior art serves as a voltage divider to provide a number of reference voltage levels.
The resistive elements of a resistive network are formed on an integrated circuit and, therefore, are subject to process variations inherent in all integrated circuit manufacture. For example, with a typical process, the resistance of a given resistive element may have a tolerance of only about .+-.5% with respect to a desired resistance. This level of accuracy is inadequate for many applications, where it is desired to have a much smaller tolerance level, e.g. .+-.1% tolerance for the resistive elements.
To obtain the desired tolerance, it has been known in the prior art to provide "trim" circuits to vary resistive parameters of the resistive network. By trimming, it is possible to provide a resistive network with the desired degree of tolerance in its resistive elements, resulting in reference voltages with a corresponding desired degree of tolerance.
In FIG. 1, a prior art trim system 10 includes a trim circuit 12 and a resistive network 14. The trim circuit 12 includes a current source 16, a transistor 18 that forms one half of a current mirror, and two trimmers 20 and 22. The current source 16 is of conventional design and is typically capable of providing approximately 10 microamperes (.mu.A) of current. The transistor 18 is, in this example, a n-channel MOSFET having its drain coupled to the output of current source 16 and having its source coupled to ground. A conductor 24 is coupled between the drain and gate of MOSFET 18 to form one half of a current mirror.
Each of the trimmers 20 and 22 include the series connection of a resistive element 26 and a transistor 28. In this example, the resistive element 26 is a oxide-silicide-oxide sandwich having one node coupled to V.sub.cc and having another node coupled to the drain of transistor 28. In this example, transistor 28 is an n-channel MOSFET transistor. The sources of both transistors 28 are coupled to ground, and the gates of transistors 28 are coupled to the gate of MOSFET 18. Therefore, as will appreciated by those skilled in the art, MOSFET 18 forms a current mirror with each of the MOSFETS 28 to provide a substantially constant reference voltage on a conductor 30 coupled to the gates of both transistors 28. A trim signal from trimmer 20 is developed between the resistive element 26 and the MOSFET 28 at a node A. A trim signal from trimmer 22 is developed between resistive element 26 and MOSFET 28 of the trimmer 22 at a node B.
The resistive network 14 includes a decoder 32 and a network 34 comprised of the series connection of a number of switch/resistor pairs 36. Each of the switch/resistor pairs 36 includes an electronic switch 38 (such as a transistor) and a resistor 40. In this instance, the decoder 32 is a 2::4 decoder which takes a signal on the two input lines 42 and decodes it into the four output lines 44. The construction of 2::4 decoders is well known to those skilled in the art. This permits the two trim signals at nodes A and B to open or close selected switches 38. The closure of a switch 38 shorts the associated resistor 40, thereby changing a resistive parameter of the network 34. As used herein "resistive parameter" or "parameter" of a resistive network means a measurable resistance between any two nodes of a network, such as network 34. This resistive parameter may be between the top and bottom of the network 34, across any one of the resistors 40, or across any series combination of resistors 40.
The trim system 10 operates as follows. An integrated circuit is manufactured having the resistive network 14 and the trim circuit 12. An ohmmeter 46 is coupled across various nodes 47 of the network 34 to measure resistive parameters. The measured resistance is then compared to a desired resistance and, if the network 34 is within tolerance specifications, the process is complete. If the measured resistance is not within the desired tolerance, a table or algorithm is consulted to determine a programming pattern for the resistive elements 26. Depending on the desired "trim", either, neither, or both of resistive elements 26 can be programmed. By "programmed" it is meant that a process of some type is performed to change the resistance of the resistive elements 26 in a discernible matter, i.e. changing the resistance by at least a couple orders of magnitude. This programming causes the trim circuit 12 to create a trim signal which controls, after being decoded by decoder 32, the switches 38 of the resistive network 14. Measurements can then be taken again with ohmmeter 46 and additional trimming can be performed, if desired or required.
There are a number of types of programmable resistive elements available in the prior art. For example, in FIG. 2a, a resistor 48 is fabricated over a semiconductor wafer substrate (not shown) and includes a base oxide layer 50, a silicide layer 52, and a top oxide layer 54. The layers 50, 52, and 54 therefore define a "sandwich" structure which is typically rectangular in configuration having a length l and a width w. The ratio of l:w is typically 15:1 to 20:1, where the width w is often in the range of 1-2 microns. The oxide layers 50 and 54 are typically silicon dioxide (SiO.sub.2), and the silicide layer 52 can be chromium silicon (CrSi). The construction of such resistive elements are well known to those skilled in the art.
The resistor 48 can be programmed with a laser beam 56. Before programming, the measured resistance between the two ends e of the resistor 48 is in the order of 1-2 kilohms. After being programmed by laser beam 56, the measured resistance between the two ends e is at least 1 megaohm. It should be noted that the laser beam 56 does not vaporize all or even a majority of the material at its point of contact but, rather, causes a recrystalization and scattering of atoms which programs the resistor 48 into a high resistance state.
In FIG. 2b, an integrated circuit capacitor 58 can also be used as a programmable resistive element. The capacitor/resistive element 58 (seen here in cross-section) typically includes a lower layer of polysilicon 60, a middle layer of silicon dioxide 62, and a top layer of polysilicon 64. Since the two polysilicon layers 60 and 64 (which are conductors) are separated by the dielectric oxide layer 62, a capacitor is formed. The resistance measured between the top t and the bottom b of the capacitor/resistive element 58 is very high in an unprogrammed state due to the oxide layer. However, when "programmed" by means of a laser beam or a high voltage applied between conductive layers 60 and 64, conductive paths are formed through the oxide layer between the polysilicon layers 60 and 64. In the unprogrammed state, the capacitor/resistive element 58 has a resistance in the order of 10 megaohms (M.OMEGA.), and after programming the capacitor/resistive element 58 can have a resistance in the range of 10 kilohms (K.OMEGA.).
In FIG. 2c, another prior art programmable resistive element is shown in cross section. An antifuse type resistive element structure 66 includes a bottom conductive layer 68, an oxide layer 70 provided with a via hole 72, and an upper conductive layer 74. The via hole 72 is filled with an antifuse material 76 such as amorphous silicon. The conductive layers are typically aluminum or aluminum alloy with a barrier coating of titanium tungsten (TiW) to prevent aluminum contamination of the amorphous silicon. When in an unprogrammed state, the resistance measured between the top t and bottom b of the antifuse structure is in the order of many megaohms. After programming the antifuse material 76 by creating a large voltage potential (e.g. 20+ volts d.c.) between layers 74 and 68, conductive pathways are formed through the antifuse material 76 lowering the resistance of the antifuse structure to the range of 100-200 ohms.
As noted above, there are variety of resistive elements that are known in the prior art to be suitable for use in integrated circuits. A common characteristic of the described programmable resistive element is that their resistance does not vary between zero and infinite resistance but, rather, vary between a small resistance and a large resistance. While traditional metal fuses, typically fabricated from aluminum in a "bow-tie" configuration, can be programmed to vary in a range from near zero resistance to near infinite resistance, metal fuses are often not preferred for us on integrated circuits due to their large size and their difficulty in programming. For example, metal fuses are difficult to laser trim due to the thickness of the metal lines. Laser energy sufficient to trim ("program") a metal fuse can often cause substrate damage.
As a result of using less-than-ideal programmable resistors, the trim circuits 12 of the prior art consume a considerable amount of current. This is because the trim signals at points A and B should swing all the way between about ground and between about V.sub.cc such that subsequent logic, such as the decoder 32, are presented with proper logical states and with minimal crowbar current. When a resistive element 26 is in its programmed (i.e. high resistance) state, at least 10 .mu.A must flow through the trimmer 20 or 22 to provide a full ground-to-V.sub.cc swing. Lower current levels will not assure this full swing, which is bad for digital logic attempting to process the trim signals. Since each of the trimmers 20 and 22 can consume 10 microamperes of current, a total of 20 microamperes may be required to operate the trim circuit 12. This amount of current can equal the total amount of current required for the remainder of the integrated circuit chip, which is clearly an undesirable situation.